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Name	Size	Permission	Date
ac97	[ DIR ]	drwxr-xr-x	2026-07-17 06:29
sof	[ DIR ]	drwxr-xr-x	2026-07-17 06:29
ac97_codec.h	15.8 KB	-rw-r--r--	2024-03-10 20:38
aci.h	2.4 KB	-rw-r--r--	2024-03-10 20:38
acp63_chip_offset_byte.h	29.75 KB	-rw-r--r--	2024-03-10 20:38
ad1816a.h	4.73 KB	-rw-r--r--	2024-03-10 20:38
ad1843.h	1.48 KB	-rw-r--r--	2024-03-10 20:38
adau1373.h	706 B	-rw-r--r--	2024-03-10 20:38
ak4113.h	10.22 KB	-rw-r--r--	2024-03-10 20:38
ak4114.h	9.54 KB	-rw-r--r--	2024-03-10 20:38
ak4117.h	8.34 KB	-rw-r--r--	2024-03-10 20:38
ak4531_codec.h	2.42 KB	-rw-r--r--	2024-03-10 20:38
ak4641.h	476 B	-rw-r--r--	2024-03-10 20:38
ak4xxx-adda.h	2.66 KB	-rw-r--r--	2024-03-10 20:38
alc5623.h	536 B	-rw-r--r--	2024-03-10 20:38
asequencer.h	3.06 KB	-rw-r--r--	2024-03-10 20:38
asound.h	590 B	-rw-r--r--	2024-03-10 20:38
asoundef.h	16.02 KB	-rw-r--r--	2024-03-10 20:38
compress_driver.h	7.8 KB	-rw-r--r--	2024-03-10 20:38
control.h	10.73 KB	-rw-r--r--	2024-03-10 20:38
core.h	15.78 KB	-rw-r--r--	2024-03-10 20:38
cs35l33.h	888 B	-rw-r--r--	2024-03-10 20:38
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cs35l56.h	10.47 KB	-rw-r--r--	2026-07-01 19:48
cs4231-regs.h	7.6 KB	-rw-r--r--	2024-03-10 20:38
cs4271.h	906 B	-rw-r--r--	2024-03-10 20:38
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designware_i2s.h	1.66 KB	-rw-r--r--	2024-03-10 20:38
dmaengine_pcm.h	6.7 KB	-rw-r--r--	2026-07-01 19:48
emu10k1.h	93.94 KB	-rw-r--r--	2026-07-01 19:48
emu10k1_synth.h	693 B	-rw-r--r--	2024-03-10 20:38
emu8000.h	3.25 KB	-rw-r--r--	2024-03-10 20:38
emu8000_reg.h	9.54 KB	-rw-r--r--	2024-03-10 20:38
emux_legacy.h	4.7 KB	-rw-r--r--	2024-03-10 20:38
emux_synth.h	6.78 KB	-rw-r--r--	2024-03-10 20:38
es1688.h	2.85 KB	-rw-r--r--	2024-03-10 20:38
graph_card.h	1.04 KB	-rw-r--r--	2024-03-10 20:38
gus.h	19.65 KB	-rw-r--r--	2024-03-10 20:38
hda-mlink.h	6.13 KB	-rw-r--r--	2024-03-10 20:38
hda_chmap.h	2.6 KB	-rw-r--r--	2024-03-10 20:38
hda_codec.h	17.75 KB	-rw-r--r--	2026-07-01 19:48
hda_component.h	2.04 KB	-rw-r--r--	2024-03-10 20:38
hda_hwdep.h	736 B	-rw-r--r--	2024-03-10 20:38
hda_i915.h	589 B	-rw-r--r--	2024-03-10 20:38
hda_register.h	11.93 KB	-rw-r--r--	2024-03-10 20:38
hda_regmap.h	6.77 KB	-rw-r--r--	2024-03-10 20:38
hda_verbs.h	16.88 KB	-rw-r--r--	2024-03-10 20:38
hdaudio.h	24.4 KB	-rw-r--r--	2024-03-10 20:38
hdaudio_ext.h	4.59 KB	-rw-r--r--	2026-07-01 19:48
hdmi-codec.h	3.04 KB	-rw-r--r--	2024-03-10 20:38
hwdep.h	1.88 KB	-rw-r--r--	2024-03-10 20:38
i2c.h	2.79 KB	-rw-r--r--	2024-03-10 20:38
info.h	7.75 KB	-rw-r--r--	2024-03-10 20:38
initval.h	2.43 KB	-rw-r--r--	2024-03-10 20:38
intel-dsp-config.h	896 B	-rw-r--r--	2024-03-10 20:38
intel-nhlt.h	3.75 KB	-rw-r--r--	2024-03-10 20:38
jack.h	3.1 KB	-rw-r--r--	2024-03-10 20:38
madera-pdata.h	1.95 KB	-rw-r--r--	2024-03-10 20:38
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max98095.h	1.33 KB	-rw-r--r--	2024-03-10 20:38
memalloc.h	3.79 KB	-rw-r--r--	2024-03-10 20:38
minors.h	3.65 KB	-rw-r--r--	2024-03-10 20:38
mixer_oss.h	1.73 KB	-rw-r--r--	2024-03-10 20:38
mpu401.h	3.81 KB	-rw-r--r--	2024-03-10 20:38
omap-hdmi-audio.h	971 B	-rw-r--r--	2024-03-10 20:38
opl3.h	11.62 KB	-rw-r--r--	2024-03-10 20:38
opl4.h	459 B	-rw-r--r--	2024-03-10 20:38
pcm-indirect.h	5.18 KB	-rw-r--r--	2024-03-10 20:38
pcm.h	54.31 KB	-rw-r--r--	2026-07-01 19:48
pcm_drm_eld.h	183 B	-rw-r--r--	2024-03-10 20:38
pcm_iec958.h	597 B	-rw-r--r--	2024-03-10 20:38
pcm_oss.h	2.01 KB	-rw-r--r--	2024-03-10 20:38
pcm_params.h	8.72 KB	-rw-r--r--	2024-03-10 20:38
pt2258.h	513 B	-rw-r--r--	2024-03-10 20:38
pxa2xx-lib.h	2.25 KB	-rw-r--r--	2024-03-10 20:38
rawmidi.h	6.01 KB	-rw-r--r--	2024-03-10 20:38
rt1015.h	283 B	-rw-r--r--	2024-03-10 20:38
rt286.h	314 B	-rw-r--r--	2024-03-10 20:38
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rt5514.h	399 B	-rw-r--r--	2024-03-10 20:38
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rt5668.h	607 B	-rw-r--r--	2024-03-10 20:38
rt5682.h	862 B	-rw-r--r--	2024-03-10 20:38
rt5682s.h	1.01 KB	-rw-r--r--	2024-03-10 20:38
sb.h	10.3 KB	-rw-r--r--	2024-03-10 20:38
sb16_csp.h	2.05 KB	-rw-r--r--	2024-03-10 20:38
sdw.h	1.63 KB	-rw-r--r--	2024-03-10 20:38
seq_device.h	2.16 KB	-rw-r--r--	2024-03-10 20:38
seq_kernel.h	3.66 KB	-rw-r--r--	2024-03-10 20:38
seq_midi_emul.h	6.6 KB	-rw-r--r--	2024-03-10 20:38
seq_midi_event.h	1.32 KB	-rw-r--r--	2024-03-10 20:38
seq_oss.h	2.21 KB	-rw-r--r--	2024-03-10 20:38
seq_oss_legacy.h	360 B	-rw-r--r--	2024-03-10 20:38
seq_virmidi.h	2.07 KB	-rw-r--r--	2024-03-10 20:38
sh_dac_audio.h	441 B	-rw-r--r--	2024-03-10 20:38
sh_fsi.h	693 B	-rw-r--r--	2024-03-10 20:38
simple_card.h	524 B	-rw-r--r--	2024-03-10 20:38
simple_card_utils.h	8.69 KB	-rw-r--r--	2024-03-10 20:38
snd_wavefront.h	5.49 KB	-rw-r--r--	2026-07-01 19:48
soc-acpi-intel-match.h	2.5 KB	-rw-r--r--	2024-03-10 20:38
soc-acpi.h	7.01 KB	-rw-r--r--	2024-03-10 20:38
soc-card.h	3.56 KB	-rw-r--r--	2024-03-10 20:38
soc-component.h	20.11 KB	-rw-r--r--	2024-03-10 20:38
soc-dai.h	20.75 KB	-rw-r--r--	2024-03-10 20:38
soc-dapm.h	33.45 KB	-rw-r--r--	2024-03-10 20:38
soc-dpcm.h	5.56 KB	-rw-r--r--	2024-03-10 20:38
soc-jack.h	3.73 KB	-rw-r--r--	2024-03-10 20:38
soc-link.h	1.14 KB	-rw-r--r--	2024-03-10 20:38
soc-topology.h	5.74 KB	-rw-r--r--	2024-03-10 20:38
soc.h	53.84 KB	-rw-r--r--	2026-07-01 19:48
sof.h	4.54 KB	-rw-r--r--	2024-03-10 20:38
soundfont.h	3.81 KB	-rw-r--r--	2024-03-10 20:38
spear_dma.h	350 B	-rw-r--r--	2024-03-10 20:38
spear_spdif.h	345 B	-rw-r--r--	2024-03-10 20:38
sta32x.h	1015 B	-rw-r--r--	2024-03-10 20:38
sta350.h	1.44 KB	-rw-r--r--	2024-03-10 20:38
tas2552-plat.h	283 B	-rw-r--r--	2024-03-10 20:38
tas2781-dsp.h	4.85 KB	-rw-r--r--	2026-07-01 19:48
tas2781-tlv.h	579 B	-rw-r--r--	2026-07-01 19:48
tas2781.h	5.27 KB	-rw-r--r--	2026-07-01 19:48
tas5086.h	210 B	-rw-r--r--	2024-03-10 20:38
tea6330t.h	468 B	-rw-r--r--	2024-03-10 20:38
timer.h	4.99 KB	-rw-r--r--	2024-03-10 20:38
tlv.h	1.59 KB	-rw-r--r--	2024-03-10 20:38
tlv320aic32x4.h	1.29 KB	-rw-r--r--	2024-03-10 20:38
tlv320dac33-plat.h	574 B	-rw-r--r--	2024-03-10 20:38
tpa6130a2-plat.h	291 B	-rw-r--r--	2024-03-10 20:38
uda1380.h	335 B	-rw-r--r--	2024-03-10 20:38
ump.h	8.14 KB	-rw-r--r--	2026-07-01 19:48
ump_convert.h	1.25 KB	-rw-r--r--	2026-07-01 19:48
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util_mem.h	1.58 KB	-rw-r--r--	2024-03-10 20:38
vx_core.h	14.7 KB	-rw-r--r--	2024-03-10 20:38
wavefront.h	16.32 KB	-rw-r--r--	2024-03-10 20:38
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Rename

/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef __SOUND_CS4231_REGS_H
#define __SOUND_CS4231_REGS_H

/*
 *  Copyright (c) by Jaroslav Kysela <perex@perex.cz>
 *  Definitions for CS4231 & InterWave chips & compatible chips registers
 */

/* IO ports */

#define CS4231P(x)		(c_d_c_CS4231##x)

#define c_d_c_CS4231REGSEL	0
#define c_d_c_CS4231REG		1
#define c_d_c_CS4231STATUS	2
#define c_d_c_CS4231PIO		3

/* codec registers */

#define CS4231_LEFT_INPUT	0x00	/* left input control */
#define CS4231_RIGHT_INPUT	0x01	/* right input control */
#define CS4231_AUX1_LEFT_INPUT	0x02	/* left AUX1 input control */
#define CS4231_AUX1_RIGHT_INPUT	0x03	/* right AUX1 input control */
#define CS4231_AUX2_LEFT_INPUT	0x04	/* left AUX2 input control */
#define CS4231_AUX2_RIGHT_INPUT	0x05	/* right AUX2 input control */
#define CS4231_LEFT_OUTPUT	0x06	/* left output control register */
#define CS4231_RIGHT_OUTPUT	0x07	/* right output control register */
#define CS4231_PLAYBK_FORMAT	0x08	/* clock and data format - playback - bits 7-0 MCE */
#define CS4231_IFACE_CTRL	0x09	/* interface control - bits 7-2 MCE */
#define CS4231_PIN_CTRL		0x0a	/* pin control */
#define CS4231_TEST_INIT	0x0b	/* test and initialization */
#define CS4231_MISC_INFO	0x0c	/* miscellaneous information */
#define CS4231_LOOPBACK		0x0d	/* loopback control */
#define CS4231_PLY_UPR_CNT	0x0e	/* playback upper base count */
#define CS4231_PLY_LWR_CNT	0x0f	/* playback lower base count */
#define CS4231_ALT_FEATURE_1	0x10	/* alternate #1 feature enable */
#define AD1845_AF1_MIC_LEFT	0x10	/* alternate #1 feature + MIC left */
#define CS4231_ALT_FEATURE_2	0x11	/* alternate #2 feature enable */
#define AD1845_AF2_MIC_RIGHT	0x11	/* alternate #2 feature + MIC right */
#define CS4231_LEFT_LINE_IN	0x12	/* left line input control */
#define CS4231_RIGHT_LINE_IN	0x13	/* right line input control */
#define CS4231_TIMER_LOW	0x14	/* timer low byte */
#define CS4231_TIMER_HIGH	0x15	/* timer high byte */
#define CS4231_LEFT_MIC_INPUT	0x16	/* left MIC input control register (InterWave only) */
#define AD1845_UPR_FREQ_SEL	0x16	/* upper byte of frequency select */
#define CS4231_RIGHT_MIC_INPUT	0x17	/* right MIC input control register (InterWave only) */
#define AD1845_LWR_FREQ_SEL	0x17	/* lower byte of frequency select */
#define CS4236_EXT_REG		0x17	/* extended register access */
#define CS4231_IRQ_STATUS	0x18	/* irq status register */
#define CS4231_LINE_LEFT_OUTPUT	0x19	/* left line output control register (InterWave only) */
#define CS4231_VERSION		0x19	/* CS4231(A) - version values */
#define CS4231_MONO_CTRL	0x1a	/* mono input/output control */
#define CS4231_LINE_RIGHT_OUTPUT 0x1b	/* right line output control register (InterWave only) */
#define AD1845_PWR_DOWN		0x1b	/* power down control */
#define CS4235_LEFT_MASTER	0x1b	/* left master output control */
#define CS4231_REC_FORMAT	0x1c	/* clock and data format - record - bits 7-0 MCE */
#define AD1845_CLOCK		0x1d	/* crystal clock select and total power down */
#define CS4235_RIGHT_MASTER	0x1d	/* right master output control */
#define CS4231_REC_UPR_CNT	0x1e	/* record upper count */
#define CS4231_REC_LWR_CNT	0x1f	/* record lower count */

/* definitions for codec register select port - CODECP( REGSEL ) */

#define CS4231_INIT		0x80	/* CODEC is initializing */
#define CS4231_MCE		0x40	/* mode change enable */
#define CS4231_TRD		0x20	/* transfer request disable */

/* definitions for codec status register - CODECP( STATUS ) */

#define CS4231_GLOBALIRQ	0x01	/* IRQ is active */

/* definitions for codec irq status */

#define CS4231_PLAYBACK_IRQ	0x10
#define CS4231_RECORD_IRQ	0x20
#define CS4231_TIMER_IRQ	0x40
#define CS4231_ALL_IRQS		0x70
#define CS4231_REC_UNDERRUN	0x08
#define CS4231_REC_OVERRUN	0x04
#define CS4231_PLY_OVERRUN	0x02
#define CS4231_PLY_UNDERRUN	0x01

/* definitions for CS4231_LEFT_INPUT and CS4231_RIGHT_INPUT registers */

#define CS4231_ENABLE_MIC_GAIN	0x20

#define CS4231_MIXS_LINE	0x00
#define CS4231_MIXS_AUX1	0x40
#define CS4231_MIXS_MIC		0x80
#define CS4231_MIXS_ALL		0xc0

/* definitions for clock and data format register - CS4231_PLAYBK_FORMAT */

#define CS4231_LINEAR_8		0x00	/* 8-bit unsigned data */
#define CS4231_ALAW_8		0x60	/* 8-bit A-law companded */
#define CS4231_ULAW_8		0x20	/* 8-bit U-law companded */
#define CS4231_LINEAR_16	0x40	/* 16-bit twos complement data - little endian */
#define CS4231_LINEAR_16_BIG	0xc0	/* 16-bit twos complement data - big endian */
#define CS4231_ADPCM_16		0xa0	/* 16-bit ADPCM */
#define CS4231_STEREO		0x10	/* stereo mode */
/* bits 3-1 define frequency divisor */
#define CS4231_XTAL1		0x00	/* 24.576 crystal */
#define CS4231_XTAL2		0x01	/* 16.9344 crystal */

/* definitions for interface control register - CS4231_IFACE_CTRL */

#define CS4231_RECORD_PIO	0x80	/* record PIO enable */
#define CS4231_PLAYBACK_PIO	0x40	/* playback PIO enable */
#define CS4231_CALIB_MODE	0x18	/* calibration mode bits */
#define CS4231_AUTOCALIB	0x08	/* auto calibrate */
#define CS4231_SINGLE_DMA	0x04	/* use single DMA channel */
#define CS4231_RECORD_ENABLE	0x02	/* record enable */
#define CS4231_PLAYBACK_ENABLE	0x01	/* playback enable */

/* definitions for pin control register - CS4231_PIN_CTRL */

#define CS4231_IRQ_ENABLE	0x02	/* enable IRQ */
#define CS4231_XCTL1		0x40	/* external control #1 */
#define CS4231_XCTL0		0x80	/* external control #0 */

/* definitions for test and init register - CS4231_TEST_INIT */

#define CS4231_CALIB_IN_PROGRESS 0x20	/* auto calibrate in progress */
#define CS4231_DMA_REQUEST	0x10	/* DMA request in progress */

/* definitions for misc control register - CS4231_MISC_INFO */

#define CS4231_MODE2		0x40	/* MODE 2 */
#define CS4231_IW_MODE3		0x6c	/* MODE 3 - InterWave enhanced mode */
#define CS4231_4236_MODE3	0xe0	/* MODE 3 - CS4236+ enhanced mode */

/* definitions for alternate feature 1 register - CS4231_ALT_FEATURE_1 */

#define	CS4231_DACZ		0x01	/* zero DAC when underrun */
#define CS4231_TIMER_ENABLE	0x40	/* codec timer enable */
#define CS4231_OLB		0x80	/* output level bit */

/* definitions for Extended Registers - CS4236+ */

#define CS4236_REG(i23val)	(((i23val << 2) & 0x10) | ((i23val >> 4) & 0x0f))
#define CS4236_I23VAL(reg)	((((reg)&0xf) << 4) | (((reg)&0x10) >> 2) | 0x8)

#define CS4236_LEFT_LINE	0x08	/* left LINE alternate volume */
#define CS4236_RIGHT_LINE	0x18	/* right LINE alternate volume */
#define CS4236_LEFT_MIC		0x28	/* left MIC volume */
#define CS4236_RIGHT_MIC	0x38	/* right MIC volume */
#define CS4236_LEFT_MIX_CTRL	0x48	/* synthesis and left input mixer control */
#define CS4236_RIGHT_MIX_CTRL	0x58	/* right input mixer control */
#define CS4236_LEFT_FM		0x68	/* left FM volume */
#define CS4236_RIGHT_FM		0x78	/* right FM volume */
#define CS4236_LEFT_DSP		0x88	/* left DSP serial port volume */
#define CS4236_RIGHT_DSP	0x98	/* right DSP serial port volume */
#define CS4236_RIGHT_LOOPBACK	0xa8	/* right loopback monitor volume */
#define CS4236_DAC_MUTE		0xb8	/* DAC mute and IFSE enable */
#define CS4236_ADC_RATE		0xc8	/* indenpendent ADC sample frequency */
#define CS4236_DAC_RATE		0xd8	/* indenpendent DAC sample frequency */
#define CS4236_LEFT_MASTER	0xe8	/* left master digital audio volume */
#define CS4236_RIGHT_MASTER	0xf8	/* right master digital audio volume */
#define CS4236_LEFT_WAVE	0x0c	/* left wavetable serial port volume */
#define CS4236_RIGHT_WAVE	0x1c	/* right wavetable serial port volume */
#define CS4236_VERSION		0x9c	/* chip version and ID */

/* definitions for extended registers - OPTI93X */
#define OPTi931_AUX_LEFT_INPUT	0x10
#define OPTi931_AUX_RIGHT_INPUT	0x11
#define OPTi93X_MIC_LEFT_INPUT	0x14
#define OPTi93X_MIC_RIGHT_INPUT	0x15
#define OPTi93X_OUT_LEFT	0x16
#define OPTi93X_OUT_RIGHT	0x17

#endif /* __SOUND_CS4231_REGS_H */