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Name	Size	Permission	Date
ac97	[ DIR ]	drwxr-xr-x	2026-07-17 06:29
sof	[ DIR ]	drwxr-xr-x	2026-07-17 06:29
ac97_codec.h	15.8 KB	-rw-r--r--	2024-03-10 20:38
aci.h	2.4 KB	-rw-r--r--	2024-03-10 20:38
acp63_chip_offset_byte.h	29.75 KB	-rw-r--r--	2024-03-10 20:38
ad1816a.h	4.73 KB	-rw-r--r--	2024-03-10 20:38
ad1843.h	1.48 KB	-rw-r--r--	2024-03-10 20:38
adau1373.h	706 B	-rw-r--r--	2024-03-10 20:38
ak4113.h	10.22 KB	-rw-r--r--	2024-03-10 20:38
ak4114.h	9.54 KB	-rw-r--r--	2024-03-10 20:38
ak4117.h	8.34 KB	-rw-r--r--	2024-03-10 20:38
ak4531_codec.h	2.42 KB	-rw-r--r--	2024-03-10 20:38
ak4641.h	476 B	-rw-r--r--	2024-03-10 20:38
ak4xxx-adda.h	2.66 KB	-rw-r--r--	2024-03-10 20:38
alc5623.h	536 B	-rw-r--r--	2024-03-10 20:38
asequencer.h	3.06 KB	-rw-r--r--	2024-03-10 20:38
asound.h	590 B	-rw-r--r--	2024-03-10 20:38
asoundef.h	16.02 KB	-rw-r--r--	2024-03-10 20:38
compress_driver.h	7.8 KB	-rw-r--r--	2024-03-10 20:38
control.h	10.73 KB	-rw-r--r--	2024-03-10 20:38
core.h	15.78 KB	-rw-r--r--	2024-03-10 20:38
cs35l33.h	888 B	-rw-r--r--	2024-03-10 20:38
cs35l34.h	741 B	-rw-r--r--	2024-03-10 20:38
cs35l35.h	2.21 KB	-rw-r--r--	2024-03-10 20:38
cs35l36.h	772 B	-rw-r--r--	2024-03-10 20:38
cs35l41.h	34.14 KB	-rw-r--r--	2024-03-10 20:38
cs35l56.h	10.47 KB	-rw-r--r--	2026-07-01 19:48
cs4231-regs.h	7.6 KB	-rw-r--r--	2024-03-10 20:38
cs4271.h	906 B	-rw-r--r--	2024-03-10 20:38
cs42l42.h	34.51 KB	-rw-r--r--	2024-03-10 20:38
cs42l43.h	385 B	-rw-r--r--	2024-03-10 20:38
cs42l52.h	592 B	-rw-r--r--	2024-03-10 20:38
cs42l56.h	1.02 KB	-rw-r--r--	2024-03-10 20:38
cs42l73.h	361 B	-rw-r--r--	2024-03-10 20:38
cs8403.h	7.95 KB	-rw-r--r--	2024-03-10 20:38
cs8427.h	9.72 KB	-rw-r--r--	2024-03-10 20:38
da7213.h	1.01 KB	-rw-r--r--	2024-03-10 20:38
da7218.h	2.41 KB	-rw-r--r--	2024-03-10 20:38
da7219-aad.h	2.37 KB	-rw-r--r--	2024-03-10 20:38
da7219.h	998 B	-rw-r--r--	2024-03-10 20:38
da9055.h	707 B	-rw-r--r--	2024-03-10 20:38
designware_i2s.h	1.66 KB	-rw-r--r--	2024-03-10 20:38
dmaengine_pcm.h	6.7 KB	-rw-r--r--	2026-07-01 19:48
emu10k1.h	93.94 KB	-rw-r--r--	2026-07-01 19:48
emu10k1_synth.h	693 B	-rw-r--r--	2024-03-10 20:38
emu8000.h	3.25 KB	-rw-r--r--	2024-03-10 20:38
emu8000_reg.h	9.54 KB	-rw-r--r--	2024-03-10 20:38
emux_legacy.h	4.7 KB	-rw-r--r--	2024-03-10 20:38
emux_synth.h	6.78 KB	-rw-r--r--	2024-03-10 20:38
es1688.h	2.85 KB	-rw-r--r--	2024-03-10 20:38
graph_card.h	1.04 KB	-rw-r--r--	2024-03-10 20:38
gus.h	19.65 KB	-rw-r--r--	2024-03-10 20:38
hda-mlink.h	6.13 KB	-rw-r--r--	2024-03-10 20:38
hda_chmap.h	2.6 KB	-rw-r--r--	2024-03-10 20:38
hda_codec.h	17.75 KB	-rw-r--r--	2026-07-01 19:48
hda_component.h	2.04 KB	-rw-r--r--	2024-03-10 20:38
hda_hwdep.h	736 B	-rw-r--r--	2024-03-10 20:38
hda_i915.h	589 B	-rw-r--r--	2024-03-10 20:38
hda_register.h	11.93 KB	-rw-r--r--	2024-03-10 20:38
hda_regmap.h	6.77 KB	-rw-r--r--	2024-03-10 20:38
hda_verbs.h	16.88 KB	-rw-r--r--	2024-03-10 20:38
hdaudio.h	24.4 KB	-rw-r--r--	2024-03-10 20:38
hdaudio_ext.h	4.59 KB	-rw-r--r--	2026-07-01 19:48
hdmi-codec.h	3.04 KB	-rw-r--r--	2024-03-10 20:38
hwdep.h	1.88 KB	-rw-r--r--	2024-03-10 20:38
i2c.h	2.79 KB	-rw-r--r--	2024-03-10 20:38
info.h	7.75 KB	-rw-r--r--	2024-03-10 20:38
initval.h	2.43 KB	-rw-r--r--	2024-03-10 20:38
intel-dsp-config.h	896 B	-rw-r--r--	2024-03-10 20:38
intel-nhlt.h	3.75 KB	-rw-r--r--	2024-03-10 20:38
jack.h	3.1 KB	-rw-r--r--	2024-03-10 20:38
madera-pdata.h	1.95 KB	-rw-r--r--	2024-03-10 20:38
max9768.h	544 B	-rw-r--r--	2024-03-10 20:38
max98088.h	1.05 KB	-rw-r--r--	2024-03-10 20:38
max98090.h	534 B	-rw-r--r--	2024-03-10 20:38
max98095.h	1.33 KB	-rw-r--r--	2024-03-10 20:38
memalloc.h	3.79 KB	-rw-r--r--	2024-03-10 20:38
minors.h	3.65 KB	-rw-r--r--	2024-03-10 20:38
mixer_oss.h	1.73 KB	-rw-r--r--	2024-03-10 20:38
mpu401.h	3.81 KB	-rw-r--r--	2024-03-10 20:38
omap-hdmi-audio.h	971 B	-rw-r--r--	2024-03-10 20:38
opl3.h	11.62 KB	-rw-r--r--	2024-03-10 20:38
opl4.h	459 B	-rw-r--r--	2024-03-10 20:38
pcm-indirect.h	5.18 KB	-rw-r--r--	2024-03-10 20:38
pcm.h	54.31 KB	-rw-r--r--	2026-07-01 19:48
pcm_drm_eld.h	183 B	-rw-r--r--	2024-03-10 20:38
pcm_iec958.h	597 B	-rw-r--r--	2024-03-10 20:38
pcm_oss.h	2.01 KB	-rw-r--r--	2024-03-10 20:38
pcm_params.h	8.72 KB	-rw-r--r--	2024-03-10 20:38
pt2258.h	513 B	-rw-r--r--	2024-03-10 20:38
pxa2xx-lib.h	2.25 KB	-rw-r--r--	2024-03-10 20:38
rawmidi.h	6.01 KB	-rw-r--r--	2024-03-10 20:38
rt1015.h	283 B	-rw-r--r--	2024-03-10 20:38
rt286.h	314 B	-rw-r--r--	2024-03-10 20:38
rt298.h	373 B	-rw-r--r--	2024-03-10 20:38
rt5514.h	399 B	-rw-r--r--	2024-03-10 20:38
rt5659.h	880 B	-rw-r--r--	2024-03-10 20:38
rt5660.h	578 B	-rw-r--r--	2024-03-10 20:38
rt5663.h	476 B	-rw-r--r--	2024-03-10 20:38
rt5665.h	723 B	-rw-r--r--	2024-03-10 20:38
rt5668.h	607 B	-rw-r--r--	2024-03-10 20:38
rt5682.h	862 B	-rw-r--r--	2024-03-10 20:38
rt5682s.h	1.01 KB	-rw-r--r--	2024-03-10 20:38
sb.h	10.3 KB	-rw-r--r--	2024-03-10 20:38
sb16_csp.h	2.05 KB	-rw-r--r--	2024-03-10 20:38
sdw.h	1.63 KB	-rw-r--r--	2024-03-10 20:38
seq_device.h	2.16 KB	-rw-r--r--	2024-03-10 20:38
seq_kernel.h	3.66 KB	-rw-r--r--	2024-03-10 20:38
seq_midi_emul.h	6.6 KB	-rw-r--r--	2024-03-10 20:38
seq_midi_event.h	1.32 KB	-rw-r--r--	2024-03-10 20:38
seq_oss.h	2.21 KB	-rw-r--r--	2024-03-10 20:38
seq_oss_legacy.h	360 B	-rw-r--r--	2024-03-10 20:38
seq_virmidi.h	2.07 KB	-rw-r--r--	2024-03-10 20:38
sh_dac_audio.h	441 B	-rw-r--r--	2024-03-10 20:38
sh_fsi.h	693 B	-rw-r--r--	2024-03-10 20:38
simple_card.h	524 B	-rw-r--r--	2024-03-10 20:38
simple_card_utils.h	8.69 KB	-rw-r--r--	2024-03-10 20:38
snd_wavefront.h	5.49 KB	-rw-r--r--	2026-07-01 19:48
soc-acpi-intel-match.h	2.5 KB	-rw-r--r--	2024-03-10 20:38
soc-acpi.h	7.01 KB	-rw-r--r--	2024-03-10 20:38
soc-card.h	3.56 KB	-rw-r--r--	2024-03-10 20:38
soc-component.h	20.11 KB	-rw-r--r--	2024-03-10 20:38
soc-dai.h	20.75 KB	-rw-r--r--	2024-03-10 20:38
soc-dapm.h	33.45 KB	-rw-r--r--	2024-03-10 20:38
soc-dpcm.h	5.56 KB	-rw-r--r--	2024-03-10 20:38
soc-jack.h	3.73 KB	-rw-r--r--	2024-03-10 20:38
soc-link.h	1.14 KB	-rw-r--r--	2024-03-10 20:38
soc-topology.h	5.74 KB	-rw-r--r--	2024-03-10 20:38
soc.h	53.84 KB	-rw-r--r--	2026-07-01 19:48
sof.h	4.54 KB	-rw-r--r--	2024-03-10 20:38
soundfont.h	3.81 KB	-rw-r--r--	2024-03-10 20:38
spear_dma.h	350 B	-rw-r--r--	2024-03-10 20:38
spear_spdif.h	345 B	-rw-r--r--	2024-03-10 20:38
sta32x.h	1015 B	-rw-r--r--	2024-03-10 20:38
sta350.h	1.44 KB	-rw-r--r--	2024-03-10 20:38
tas2552-plat.h	283 B	-rw-r--r--	2024-03-10 20:38
tas2781-dsp.h	4.85 KB	-rw-r--r--	2026-07-01 19:48
tas2781-tlv.h	579 B	-rw-r--r--	2026-07-01 19:48
tas2781.h	5.27 KB	-rw-r--r--	2026-07-01 19:48
tas5086.h	210 B	-rw-r--r--	2024-03-10 20:38
tea6330t.h	468 B	-rw-r--r--	2024-03-10 20:38
timer.h	4.99 KB	-rw-r--r--	2024-03-10 20:38
tlv.h	1.59 KB	-rw-r--r--	2024-03-10 20:38
tlv320aic32x4.h	1.29 KB	-rw-r--r--	2024-03-10 20:38
tlv320dac33-plat.h	574 B	-rw-r--r--	2024-03-10 20:38
tpa6130a2-plat.h	291 B	-rw-r--r--	2024-03-10 20:38
uda1380.h	335 B	-rw-r--r--	2024-03-10 20:38
ump.h	8.14 KB	-rw-r--r--	2026-07-01 19:48
ump_convert.h	1.25 KB	-rw-r--r--	2026-07-01 19:48
ump_msg.h	13.81 KB	-rw-r--r--	2026-07-01 19:48
util_mem.h	1.58 KB	-rw-r--r--	2024-03-10 20:38
vx_core.h	14.7 KB	-rw-r--r--	2024-03-10 20:38
wavefront.h	16.32 KB	-rw-r--r--	2024-03-10 20:38
wm0010.h	321 B	-rw-r--r--	2024-03-10 20:38
wm2000.h	479 B	-rw-r--r--	2024-03-10 20:38
wm2200.h	1.21 KB	-rw-r--r--	2024-03-10 20:38
wm5100.h	935 B	-rw-r--r--	2024-03-10 20:38
wm8903.h	15.02 KB	-rw-r--r--	2024-03-10 20:38
wm8904.h	7.22 KB	-rw-r--r--	2024-03-10 20:38
wm8955.h	442 B	-rw-r--r--	2024-03-10 20:38
wm8960.h	888 B	-rw-r--r--	2024-03-10 20:38
wm8962.h	1.65 KB	-rw-r--r--	2024-03-10 20:38
wm8993.h	1.05 KB	-rw-r--r--	2024-03-10 20:38
wm8996.h	1.19 KB	-rw-r--r--	2024-03-10 20:38
wm9081.h	515 B	-rw-r--r--	2024-03-10 20:38
wm9090.h	634 B	-rw-r--r--	2024-03-10 20:38
wss.h	7.76 KB	-rw-r--r--	2024-03-10 20:38

Rename

/* SPDX-License-Identifier: GPL-2.0-or-later */
#ifndef __SOUND_AK4117_H
#define __SOUND_AK4117_H

/*
 *  Routines for Asahi Kasei AK4117
 *  Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
 */

#define AK4117_REG_PWRDN	0x00	/* power down */
#define AK4117_REG_CLOCK	0x01	/* clock control */
#define AK4117_REG_IO		0x02	/* input/output control */
#define AK4117_REG_INT0_MASK	0x03	/* interrupt0 mask */
#define AK4117_REG_INT1_MASK	0x04	/* interrupt1 mask */
#define AK4117_REG_RCS0		0x05	/* receiver status 0 */
#define AK4117_REG_RCS1		0x06	/* receiver status 1 */
#define AK4117_REG_RCS2		0x07	/* receiver status 2 */
#define AK4117_REG_RXCSB0	0x08	/* RX channel status byte 0 */
#define AK4117_REG_RXCSB1	0x09	/* RX channel status byte 1 */
#define AK4117_REG_RXCSB2	0x0a	/* RX channel status byte 2 */
#define AK4117_REG_RXCSB3	0x0b	/* RX channel status byte 3 */
#define AK4117_REG_RXCSB4	0x0c	/* RX channel status byte 4 */
#define AK4117_REG_Pc0		0x0d	/* burst preamble Pc byte 0 */
#define AK4117_REG_Pc1		0x0e	/* burst preamble Pc byte 1 */
#define AK4117_REG_Pd0		0x0f	/* burst preamble Pd byte 0 */
#define AK4117_REG_Pd1		0x10	/* burst preamble Pd byte 1 */
#define AK4117_REG_QSUB_ADDR	0x11	/* Q-subcode address + control */
#define AK4117_REG_QSUB_TRACK	0x12	/* Q-subcode track */
#define AK4117_REG_QSUB_INDEX	0x13	/* Q-subcode index */
#define AK4117_REG_QSUB_MINUTE	0x14	/* Q-subcode minute */
#define AK4117_REG_QSUB_SECOND	0x15	/* Q-subcode second */
#define AK4117_REG_QSUB_FRAME	0x16	/* Q-subcode frame */
#define AK4117_REG_QSUB_ZERO	0x17	/* Q-subcode zero */
#define AK4117_REG_QSUB_ABSMIN	0x18	/* Q-subcode absolute minute */
#define AK4117_REG_QSUB_ABSSEC	0x19	/* Q-subcode absolute second */
#define AK4117_REG_QSUB_ABSFRM	0x1a	/* Q-subcode absolute frame */

/* sizes */
#define AK4117_REG_RXCSB_SIZE	((AK4117_REG_RXCSB4-AK4117_REG_RXCSB0)+1)
#define AK4117_REG_QSUB_SIZE	((AK4117_REG_QSUB_ABSFRM-AK4117_REG_QSUB_ADDR)+1)

/* AK4117_REG_PWRDN bits */
#define AK4117_EXCT		(1<<4)	/* 0 = X'tal mode, 1 = external clock mode */
#define AK4117_XTL1		(1<<3)	/* XTL1=0,XTL0=0 -> 11.2896Mhz; XTL1=0,XTL0=1 -> 12.288Mhz */
#define AK4117_XTL0		(1<<2)	/* XTL1=1,XTL0=0 -> 24.576Mhz; XTL1=1,XTL0=1 -> use channel status */
#define AK4117_XTL_11_2896M	(0)
#define AK4117_XTL_12_288M	AK4117_XTL0
#define AK4117_XTL_24_576M	AK4117_XTL1
#define AK4117_XTL_EXT		(AK4117_XTL1|AK4117_XTL0)
#define AK4117_PWN		(1<<1)	/* 0 = power down, 1 = normal operation */
#define AK4117_RST		(1<<0)	/* 0 = reset & initialize (except this register), 1 = normal operation */

/* AK4117_REQ_CLOCK bits */
#define AK4117_LP		(1<<7)	/* 0 = normal mode, 1 = low power mode (Fs up to 48kHz only) */
#define AK4117_PKCS1		(1<<6)	/* master clock frequency at PLL mode (when LP == 0) */
#define AK4117_PKCS0		(1<<5)
#define AK4117_PKCS_512fs	(0)
#define AK4117_PKCS_256fs	AK4117_PKCS0
#define AK4117_PKCS_128fs	AK4117_PKCS1
#define AK4117_DIV		(1<<4)	/* 0 = MCKO == Fs, 1 = MCKO == Fs / 2; X'tal mode only */
#define AK4117_XCKS1		(1<<3)	/* master clock frequency at X'tal mode */
#define AK4117_XCKS0		(1<<2)
#define AK4117_XCKS_128fs	(0)
#define AK4117_XCKS_256fs	AK4117_XCKS0
#define AK4117_XCKS_512fs	AK4117_XCKS1
#define AK4117_XCKS_1024fs	(AK4117_XCKS1|AK4117_XCKS0)
#define AK4117_CM1		(1<<1)	/* MCKO operation mode select */
#define AK4117_CM0		(1<<0)
#define AK4117_CM_PLL		(0)		/* use RX input as master clock */
#define AK4117_CM_XTAL		(AK4117_CM0)	/* use X'tal as master clock */
#define AK4117_CM_PLL_XTAL	(AK4117_CM1)	/* use Rx input but X'tal when PLL loses lock */
#define AK4117_CM_MONITOR	(AK4117_CM0|AK4117_CM1) /* use X'tal as master clock, but use PLL for monitoring */

/* AK4117_REG_IO */
#define AK4117_IPS		(1<<7)	/* Input Recovery Data Select, 0 = RX0, 1 = RX1 */
#define AK4117_UOUTE		(1<<6)	/* U-bit output enable to UOUT, 0 = disable, 1 = enable */
#define AK4117_CS12		(1<<5)	/* channel status select, 0 = channel1, 1 = channel2 */
#define AK4117_EFH2		(1<<4)	/* INT0 pin hold count select */
#define AK4117_EFH1		(1<<3)
#define AK4117_EFH_512LRCLK	(0)
#define AK4117_EFH_1024LRCLK	(AK4117_EFH1)
#define AK4117_EFH_2048LRCLK	(AK4117_EFH2)
#define AK4117_EFH_4096LRCLK	(AK4117_EFH1|AK4117_EFH2)
#define AK4117_DIF2		(1<<2)	/* audio data format control */
#define AK4117_DIF1		(1<<1)
#define AK4117_DIF0		(1<<0)
#define AK4117_DIF_16R		(0)				/* STDO: 16-bit, right justified */
#define AK4117_DIF_18R		(AK4117_DIF0)			/* STDO: 18-bit, right justified */
#define AK4117_DIF_20R		(AK4117_DIF1)			/* STDO: 20-bit, right justified */
#define AK4117_DIF_24R		(AK4117_DIF1|AK4117_DIF0)	/* STDO: 24-bit, right justified */
#define AK4117_DIF_24L		(AK4117_DIF2)			/* STDO: 24-bit, left justified */
#define AK4117_DIF_24I2S	(AK4117_DIF2|AK4117_DIF0)	/* STDO: I2S */

/* AK4117_REG_INT0_MASK & AK4117_REG_INT1_MASK */
#define AK4117_MULK		(1<<7)	/* mask enable for UNLOCK bit */
#define AK4117_MPAR		(1<<6)	/* mask enable for PAR bit */
#define AK4117_MAUTO		(1<<5)	/* mask enable for AUTO bit */
#define AK4117_MV		(1<<4)	/* mask enable for V bit */
#define AK4117_MAUD		(1<<3)	/* mask enable for AUDION bit */
#define AK4117_MSTC		(1<<2)	/* mask enable for STC bit */
#define AK4117_MCIT		(1<<1)	/* mask enable for CINT bit */
#define AK4117_MQIT		(1<<0)	/* mask enable for QINT bit */

/* AK4117_REG_RCS0 */
#define AK4117_UNLCK		(1<<7)	/* PLL lock status, 0 = lock, 1 = unlock */
#define AK4117_PAR		(1<<6)	/* parity error or biphase error status, 0 = no error, 1 = error */
#define AK4117_AUTO		(1<<5)	/* Non-PCM or DTS stream auto detection, 0 = no detect, 1 = detect */
#define AK4117_V		(1<<4)	/* Validity bit, 0 = valid, 1 = invalid */
#define AK4117_AUDION		(1<<3)	/* audio bit output, 0 = audio, 1 = non-audio */
#define AK4117_STC		(1<<2)	/* sampling frequency or Pre-emphasis change, 0 = no detect, 1 = detect */
#define AK4117_CINT		(1<<1)	/* channel status buffer interrupt, 0 = no change, 1 = change */
#define AK4117_QINT		(1<<0)	/* Q-subcode buffer interrupt, 0 = no change, 1 = changed */

/* AK4117_REG_RCS1 */
#define AK4117_DTSCD		(1<<6)	/* DTS-CD bit audio stream detect, 0 = no detect, 1 = detect */
#define AK4117_NPCM		(1<<5)	/* Non-PCM bit stream detection, 0 = no detect, 1 = detect */
#define AK4117_PEM		(1<<4)	/* Pre-emphasis detect, 0 = OFF, 1 = ON */
#define AK4117_FS3		(1<<3)	/* sampling frequency detection */
#define AK4117_FS2		(1<<2)
#define AK4117_FS1		(1<<1)
#define AK4117_FS0		(1<<0)
#define AK4117_FS_44100HZ	(0)
#define AK4117_FS_48000HZ	(AK4117_FS1)
#define AK4117_FS_32000HZ	(AK4117_FS1|AK4117_FS0)
#define AK4117_FS_88200HZ	(AK4117_FS3)
#define AK4117_FS_96000HZ	(AK4117_FS3|AK4117_FS1)
#define AK4117_FS_176400HZ	(AK4117_FS3|AK4117_FS2)
#define AK4117_FS_192000HZ	(AK4117_FS3|AK4117_FS2|AK4117_FS1)

/* AK4117_REG_RCS2 */
#define AK4117_CCRC		(1<<1)	/* CRC for channel status, 0 = no error, 1 = error */
#define AK4117_QCRC		(1<<0)	/* CRC for Q-subcode, 0 = no error, 1 = error */

/* flags for snd_ak4117_check_rate_and_errors() */
#define AK4117_CHECK_NO_STAT	(1<<0)	/* no statistics */
#define AK4117_CHECK_NO_RATE	(1<<1)	/* no rate check */

#define AK4117_CONTROLS		13

typedef void (ak4117_write_t)(void *private_data, unsigned char addr, unsigned char data);
typedef unsigned char (ak4117_read_t)(void *private_data, unsigned char addr);

enum {
	AK4117_PARITY_ERRORS,
	AK4117_V_BIT_ERRORS,
	AK4117_QCRC_ERRORS,
	AK4117_CCRC_ERRORS,
	AK4117_NUM_ERRORS
};

struct ak4117 {
	struct snd_card *card;
	ak4117_write_t * write;
	ak4117_read_t * read;
	void * private_data;
	unsigned int init: 1;
	spinlock_t lock;
	unsigned char regmap[5];
	struct snd_kcontrol *kctls[AK4117_CONTROLS];
	struct snd_pcm_substream *substream;
	unsigned long errors[AK4117_NUM_ERRORS];
	unsigned char rcs0;
	unsigned char rcs1;
	unsigned char rcs2;
	struct timer_list timer;	/* statistic timer */
	void *change_callback_private;
	void (*change_callback)(struct ak4117 *ak4117, unsigned char c0, unsigned char c1);
};

int snd_ak4117_create(struct snd_card *card, ak4117_read_t *read, ak4117_write_t *write,
		      const unsigned char pgm[5], void *private_data, struct ak4117 **r_ak4117);
void snd_ak4117_reg_write(struct ak4117 *ak4117, unsigned char reg, unsigned char mask, unsigned char val);
void snd_ak4117_reinit(struct ak4117 *ak4117);
int snd_ak4117_build(struct ak4117 *ak4117, struct snd_pcm_substream *capture_substream);
int snd_ak4117_external_rate(struct ak4117 *ak4117);
int snd_ak4117_check_rate_and_errors(struct ak4117 *ak4117, unsigned int flags);

#endif /* __SOUND_AK4117_H */