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Name	Size	Permission	Date
davinci	[ DIR ]	drwxr-xr-x	2026-06-04 06:36
drv-intf	[ DIR ]	drwxr-xr-x	2026-06-04 06:36
i2c	[ DIR ]	drwxr-xr-x	2026-06-04 06:36
tpg	[ DIR ]	drwxr-xr-x	2026-06-04 06:36
cec-notifier.h	5.03 KB	-rw-r--r--	2024-03-10 20:38
cec-pin.h	2.79 KB	-rw-r--r--	2024-03-10 20:38
cec.h	17.08 KB	-rw-r--r--	2026-05-26 09:55
demux.h	22.69 KB	-rw-r--r--	2024-03-10 20:38
dmxdev.h	5.87 KB	-rw-r--r--	2024-03-10 20:38
dvb-usb-ids.h	19.46 KB	-rw-r--r--	2024-03-10 20:38
dvb_ca_en50221.h	4.35 KB	-rw-r--r--	2024-03-10 20:38
dvb_demux.h	10.77 KB	-rw-r--r--	2024-03-10 20:38
dvb_frontend.h	30.42 KB	-rw-r--r--	2024-03-10 20:38
dvb_net.h	2.43 KB	-rw-r--r--	2024-03-10 20:38
dvb_ringbuffer.h	8.32 KB	-rw-r--r--	2024-03-10 20:38
dvb_vb2.h	7.65 KB	-rw-r--r--	2024-03-10 20:38
dvbdev.h	14.77 KB	-rw-r--r--	2024-03-10 20:38
frame_vector.h	1.42 KB	-rw-r--r--	2024-03-10 20:38
imx.h	190 B	-rw-r--r--	2024-03-10 20:38
ipu-bridge.h	4.27 KB	-rw-r--r--	2024-03-10 20:38
jpeg.h	500 B	-rw-r--r--	2024-03-10 20:38
media-dev-allocator.h	2.21 KB	-rw-r--r--	2024-03-10 20:38
media-device.h	17.52 KB	-rw-r--r--	2024-03-10 20:38
media-devnode.h	5.29 KB	-rw-r--r--	2024-03-10 20:38
media-entity.h	47.31 KB	-rw-r--r--	2026-05-26 09:55
media-request.h	11.96 KB	-rw-r--r--	2024-03-10 20:38
mipi-csi2.h	1.46 KB	-rw-r--r--	2024-03-10 20:38
rc-core.h	12.15 KB	-rw-r--r--	2024-03-10 20:38
rc-map.h	14.47 KB	-rw-r--r--	2024-03-10 20:38
rcar-fcp.h	1.1 KB	-rw-r--r--	2024-03-10 20:38
tuner-types.h	7.54 KB	-rw-r--r--	2024-03-10 20:38
tuner.h	8.43 KB	-rw-r--r--	2024-03-10 20:38
tveeprom.h	3.3 KB	-rw-r--r--	2024-03-10 20:38
v4l2-async.h	11.67 KB	-rw-r--r--	2024-03-10 20:38
v4l2-cci.h	4.75 KB	-rw-r--r--	2024-03-10 20:38
v4l2-common.h	19.96 KB	-rw-r--r--	2026-05-26 09:55
v4l2-ctrls.h	54.48 KB	-rw-r--r--	2024-03-10 20:38
v4l2-dev.h	20.11 KB	-rw-r--r--	2024-03-10 20:38
v4l2-device.h	18.46 KB	-rw-r--r--	2024-03-10 20:38
v4l2-dv-timings.h	9.32 KB	-rw-r--r--	2026-05-26 09:55
v4l2-event.h	6.01 KB	-rw-r--r--	2024-03-10 20:38
v4l2-fh.h	4.22 KB	-rw-r--r--	2024-03-10 20:38
v4l2-flash-led-class.h	5.75 KB	-rw-r--r--	2024-03-10 20:38
v4l2-fwnode.h	15.57 KB	-rw-r--r--	2024-03-10 20:38
v4l2-h264.h	3.1 KB	-rw-r--r--	2024-03-10 20:38
v4l2-image-sizes.h	827 B	-rw-r--r--	2024-03-10 20:38
v4l2-ioctl.h	33.31 KB	-rw-r--r--	2024-03-10 20:38
v4l2-jpeg.h	5.08 KB	-rw-r--r--	2024-03-10 20:38
v4l2-mc.h	7.68 KB	-rw-r--r--	2024-03-10 20:38
v4l2-mediabus.h	8.76 KB	-rw-r--r--	2024-03-10 20:38
v4l2-mem2mem.h	29.27 KB	-rw-r--r--	2026-05-26 09:55
v4l2-rect.h	5.71 KB	-rw-r--r--	2024-03-10 20:38
v4l2-subdev.h	71.43 KB	-rw-r--r--	2026-05-26 09:55
v4l2-vp9.h	8.32 KB	-rw-r--r--	2024-03-10 20:38
videobuf2-core.h	50.44 KB	-rw-r--r--	2026-05-26 09:55
videobuf2-dma-contig.h	883 B	-rw-r--r--	2024-03-10 20:38
videobuf2-dma-sg.h	698 B	-rw-r--r--	2024-03-10 20:38
videobuf2-dvb.h	1.81 KB	-rw-r--r--	2024-03-10 20:38
videobuf2-memops.h	1.09 KB	-rw-r--r--	2024-03-10 20:38
videobuf2-v4l2.h	14.39 KB	-rw-r--r--	2024-03-10 20:38
videobuf2-vmalloc.h	509 B	-rw-r--r--	2024-03-10 20:38
vsp1.h	3.62 KB	-rw-r--r--	2024-03-10 20:38

Rename

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * MIPI Camera Control Interface (CCI) register access helpers.
 *
 * Copyright (C) 2023 Hans de Goede <hansg@kernel.org>
 */
#ifndef _V4L2_CCI_H
#define _V4L2_CCI_H

#include <linux/bitfield.h>
#include <linux/bits.h>
#include <linux/types.h>

struct i2c_client;
struct regmap;

/**
 * struct cci_reg_sequence - An individual write from a sequence of CCI writes
 *
 * @reg: Register address, use CCI_REG#() macros to encode reg width
 * @val: Register value
 *
 * Register/value pairs for sequences of writes.
 */
struct cci_reg_sequence {
	u32 reg;
	u64 val;
};

/*
 * Macros to define register address with the register width encoded
 * into the higher bits.
 */
#define CCI_REG_ADDR_MASK		GENMASK(15, 0)
#define CCI_REG_WIDTH_SHIFT		16
#define CCI_REG_WIDTH_MASK		GENMASK(19, 16)
/*
 * Private CCI register flags, for the use of drivers.
 */
#define CCI_REG_PRIVATE_SHIFT		28U
#define CCI_REG_PRIVATE_MASK		GENMASK(31U, CCI_REG_PRIVATE_SHIFT)

#define CCI_REG_WIDTH_BYTES(x)		FIELD_GET(CCI_REG_WIDTH_MASK, x)
#define CCI_REG_WIDTH(x)		(CCI_REG_WIDTH_BYTES(x) << 3)
#define CCI_REG_ADDR(x)			FIELD_GET(CCI_REG_ADDR_MASK, x)
#define CCI_REG_LE			BIT(20)

/**
 * cci_read() - Read a value from a single CCI register
 *
 * @map: Register map to read from
 * @reg: Register address to read, use CCI_REG#() macros to encode reg width
 * @val: Pointer to store read value
 * @err: Optional pointer to store errors, if a previous error is set
 *       then the read will be skipped
 *
 * Return: %0 on success or a negative error code on failure.
 */
int cci_read(struct regmap *map, u32 reg, u64 *val, int *err);

/**
 * cci_write() - Write a value to a single CCI register
 *
 * @map: Register map to write to
 * @reg: Register address to write, use CCI_REG#() macros to encode reg width
 * @val: Value to be written
 * @err: Optional pointer to store errors, if a previous error is set
 *       then the write will be skipped
 *
 * Return: %0 on success or a negative error code on failure.
 */
int cci_write(struct regmap *map, u32 reg, u64 val, int *err);

/**
 * cci_update_bits() - Perform a read/modify/write cycle on
 *                     a single CCI register
 *
 * @map: Register map to update
 * @reg: Register address to update, use CCI_REG#() macros to encode reg width
 * @mask: Bitmask to change
 * @val: New value for bitmask
 * @err: Optional pointer to store errors, if a previous error is set
 *       then the update will be skipped
 *
 * Note this uses read-modify-write to update the bits, atomicity with regards
 * to other cci_*() register access functions is NOT guaranteed.
 *
 * Return: %0 on success or a negative error code on failure.
 */
int cci_update_bits(struct regmap *map, u32 reg, u64 mask, u64 val, int *err);

/**
 * cci_multi_reg_write() - Write multiple registers to the device
 *
 * @map: Register map to write to
 * @regs: Array of structures containing register-address, -value pairs to be
 *        written, register-addresses use CCI_REG#() macros to encode reg width
 * @num_regs: Number of registers to write
 * @err: Optional pointer to store errors, if a previous error is set
 *       then the write will be skipped
 *
 * Write multiple registers to the device where the set of register, value
 * pairs are supplied in any order, possibly not all in a single range.
 *
 * Use of the CCI_REG#() macros to encode reg width is mandatory.
 *
 * For raw lists of register-address, -value pairs with only 8 bit
 * wide writes regmap_multi_reg_write() can be used instead.
 *
 * Return: %0 on success or a negative error code on failure.
 */
int cci_multi_reg_write(struct regmap *map, const struct cci_reg_sequence *regs,
			unsigned int num_regs, int *err);

#if IS_ENABLED(CONFIG_V4L2_CCI_I2C)
/**
 * devm_cci_regmap_init_i2c() - Create regmap to use with cci_*() register
 *                              access functions
 *
 * @client: i2c_client to create the regmap for
 * @reg_addr_bits: register address width to use (8 or 16)
 *
 * Note the memory for the created regmap is devm() managed, tied to the client.
 *
 * Return: %0 on success or a negative error code on failure.
 */
struct regmap *devm_cci_regmap_init_i2c(struct i2c_client *client,
					int reg_addr_bits);
#endif

#endif